Researchers have developed an innovative method known as step-necking growth for creating ultrathin silicon nanowire (SiNW) channels, which hold promise for enhancing the performance and scalability of field effect transistors (FETs). With diameters less than 30 nm and lengths under 100 nm, these SiNWs are considered ideal for high-performance electronic applications, including large-area displays and sensors.
Traditionally, the manufacturing of such delicate and precise channels has relied heavily on high-precision lithography techniques, which are often incompatible with large area electronics. This has posed challenges, especially when attempting to fabricate narrow channels with specific characteristics. The step-necking growth method emerges as a groundbreaking solution, showcasing how silicon nanowires can be engineered without necessitating costly and complex fabrication techniques.
According to the authors of the article, "These findings mark the pioneer experimental demonstration of catalytic growth acting as a deterministic fabrication method for precisely crafting engineered FET channels, ideally fitting the requirements of high-performance large-area displays and sensors." The process involves manipulating the growth of the nanowires using metal droplets, which effectively modulate the geometry of the silicon nanowires at designated locations.
During the study, the researchers demonstrated how the necking dynamic occurs when the leading droplet of the growing silicon wire stretches and jumps over crossing steps. This local curvature effect produces short necking segments of less than 100 nm, narrowing the diameter significantly from about 45 nm to below 25 nm. The result is FETs with enhanced on/off current ratios exceeding 8 × 107 and sharper subthreshold swing values, recorded at 70 mV/decade.
The construction of these step-necked silicon nanowire FETs involved the utilization of metal-droplet-mediated catalytic growth, which has proven to be cost-effective and efficient. The study tackled the limitations of existing manufacturing methods, thereby paving the way for new advancements within the field. The ability to seamlessly integrate thicker segments at both ends of the channel facilitates improved source and drain contacts, contributing to the overall performance enhancements.
The experimental results were conclusive, showcasing practical implementations of this method across multiple independent growth experiments. The success of the necking channel designs reflects the researchers' capacity to overcome longstanding challenges associated with nanowire growth, echoing their optimism about the future applications of such advanced semiconductor technologies.
Looking forward, this research signifies major strides toward advancing large-area electronics. The authors propose this step-necking growth technique as not only scalable but also as filling the current gaps within semiconductor fabrication technology.
Concluding the discussion, one of the key outcomes highlights the advancement of necked-channel FETs, which delivered exceptional characteristics—specifically, "The necking channel FETs achieve a high on-current of 32 μA/μm and a sharp SS of 70 mV/dec." This showcases how the step-necking growth method can vastly improve the operating efficiency of transistors, an exciting prospect for future developments within the field.